Miscellaneous features Summer 2025

[tomcl]

Working list to be finalised before end of Summer Term 2025 and used for dev over Summer vacation.

• 1a Fix #507 DONE
• 1b Add breadcrumb + search box selector to Waveform simulator (improve / PR HLP efforts) DONE
• 1c Improve parameters (PR HLP – improve as needed)
• 1d Add scroll bars to truth tables #513 DONE
• 1e Fix #510, #511
• 1f Add #515
• 1g Add #519
• 2a Get fsdocs documentation working properly (this is easy). Improve it a bit (also easy). See #508 . DONE
• 2b Improve project open /create dialog
  • Open: show all projects with details within a given file system directory
    • Display current directory full path
    • Display projects in current directory - with click to open
    • Display direct subdirectories of current directory as breadcrumb-like buttons with number of contained projects anywhere inside and highlight if that number is non-zero. Clicking on them changes current subdirectory.
    • Choose subdirectory as system default or subdirectory above last opened project
    • Have buttons for moving to parent of current directory
  • Create: use popup to define directory and name
• 2c Redo menus with a nice Issie menu generator equiv to the built-in one or better. Remove the built-in menus.
• 3a Implement standard and external library mechanism using parametrized Issie components.
• 3b Fix: wire separation not idempotent and alters sheet
  • Problem is that tiny changes that should not be recorded now alter wire positions
  • Possible solution in two parts
    • 1 Make wire separation idempotent
    • 2 Store only manually routed segments. Create connections on open by autorouting all and then manually fixing segments and then running separation.
• 3c Fix: sheets that have wrongly routed wires. On load, check all wires for sanity.
  • This feature would be better after 3b is fixed
  • Sanity defined by wires start/end on ports. Maybe some additional criteria. e.g. different nets cannot overlap.
  • If any wire is not sane autoroute it, then reseparate all wires.
  • Or maybe reseparate it and adjacent wires only.
  • Maybe throw up a confirmation prompt so doing this is under under control.
  • Maybe do this only on project load (not on sheet load)
• 4 Refactor Issie so that design sheets have a more rational set of data structures: reduce load/save technical debt.
• 5a Implement ifThenElse components and forLoop subsheets
• 5b Make Verilog code generation output from Issie components properly readable.
• 5c Improve Verilog parsing (likely this is beyond scope). Verilog parser stuff depends on result of FYP known at end of June.
• 6 Add reveal-on-mouseover to waveforms #509 DONE

[tomcl]

Scheduling and assignment still TBC