Display output vs dispen timing isn't quite right

[tom-seddon]

Mode 7 in b2:

Mode 7 on a beeb: (blue is DISPEN - monitor is TTL RGB, its blue input is attached to the video ULA's dispen pin)

There's an extra 1 microsec delay that isn't being accounted for...

[tom-seddon]

Also, mode 4. Note the extra column after dispen goes to 0.

Mode 2. Perhaps not super obvious from this crap pic, but there's 1 additional column here too after dispen goes to 0.

[tom-seddon]

For bitmap modes: I guess the video ULA can't start to shift data out until it's read the data in. It must take 1 cycle for that to happen, perhaps?

So for the top left byte in Mode 4, the period when DISPEN=1 and MAx/RAx=$5800 is occupied by the video ULA latching that byte in, and shifting out nothing. (Presumably when DISPEN=0, it sets its latch to 0.)

And so you don't get to see the contents of $5800 until 1 byte's-worth of time later, when the CRTC outputs refer to $5808. And so on.

For teletext modes: b2 will be modelling the ~3 microsec SAA5050 delay incorrectly... probably? I don't feel like I understand the timing here any more...