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Circuit Design
I've wondered whether a design space exists for optimizing circuits to maximize XOR gates, or rather, minimize AND gates. From what I can gather, most of the circuits out there were generated using some sort of chip design software from Synopsys. I imagine that software is written for very different design contraints compared to garbled circuits, e.g. surface area.
Could be something interesting to look into.
TLS PRF consists almost exclusively of SHA256. Both sha256 and aes128 from kuleuven website were optimized for AND gates.
I see. I'm curious to understand how they were optimized
Closing, this is an interesting topic but not worth keeping an issue open for it.