virgil
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titzer
I wonder if it is feasible to add ARM backend for virgil
Hi,
I'm looking for a VM that can run a PLC. The idea is:
- Have some kind of high level IDE (disclaimer. I build one: https://github.com/vlsi/ide61131)
- Make that IDE to compile the program into some kind of bytecode
- Make PLC to execute that bytecode
The bytecode is there so IDE, etc can be PLC-independent (that is one can easily support different kinds of CPUs without changing front-end too much).
I do like virgil's idea of "allocating all the memory at initialization".
For the "OS" I think of http://www.freertos.org/ (that will provide TCP/UDP, and some multitasking).
I aim for 200KiB...1MiB RAM devices with 200Mhz+ cpus. I aim to fit "simple logic computation" under 1ms.
The devices might have different CPUs (some kind of ARM, AURIX) and common denominator is probably some kind of C compiler (gcc, TI, Keil, etc).
Is virgil feasible/reasonable for that?
@titzer , sorry for mentioning you directly, but I just want to check if you saw the question regarding virgil usage in a embedded device as a "main scripting language".
Hi @vlsi, I have been working on an arm backend in a branch. The instruction selector is almost finished, but I am using a new code generator which will require a new register allocator, which I haven't gotten around to yet.
That said, Virgil has no problem fitting into the size constraints to you mentioned. The smallest possible Virgil program is about 300 bytes of code without using any RAM at all (except for the stack). If you use the GC, then that takes another 4KB of code, and you can set the heap size as small as you like, even on the order of KB. If you don't use the GC, then you don't need to compile it in, and can have all your data structures allocated at compile time.
