Enable ice40 PLL for ice40_up5k_b_evn board

[kamejoko80]

Hello,

I've tried to increase the sys_clk frequency for the ice40_up5k_b_evn board as below:

class _CRG(Module): def init(self, platform): clk12 = platform.request("clk12")

    self.clock_domains.cd_sys = ClockDomain()
    self.reset = Signal()

    # FIXME: Use PLL, increase system clock to 32 MHz, pending nextpnr
    # fixes.
    # Fout = Fin x (DIVF + 1) / (2^DIVQ x (DIVR + 1))
    self.specials += \
        Instance("SB_PLL40_2_PAD",
            p_FEEDBACK_PATH="SIMPLE",
            p_DIVR=0,         # 0
            p_DIVF=3,         # 3
            p_DIVQ=1,         # 1 => Fout = 2 x Fin = 24MHz
            p_FILTER_RANGE=2,
            i_RESETB=1,
            i_BYPASS=0,                
            i_PACKAGEPIN=clk12,
            o_PLLOUTCOREA=self.cd_sys.clk,
        )
    # self.comb += self.cd_sys.clk.eq(clk12)
    
    # POR reset logic- POR generated from sys clk, POR logic feeds sys clk
    # reset.
    self.clock_domains.cd_por = ClockDomain()
    reset_delay = Signal(12, reset=4095)
    self.comb += [
        self.cd_por.clk.eq(self.cd_sys.clk),
        self.cd_sys.rst.eq(reset_delay != 0)
    ]
    self.sync.por += \
        If(reset_delay != 0,
            reset_delay.eq(reset_delay - 1)
        )
    self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)

Then I also changed clk_freq = int(24e6) in BaseSoC class, after downloading the bitstream the CPU seems worked properly however the UART prints out unreadable characters on the terminal.

My CPU details configuration as below:

export PLATFORM=ice40_up5k_b_evn export TARGET=base export CPU=vexriscv export CPU_VARIANT=min export FIRMWARE=micropython

I don't how to fix it, have you ever tried to increase the ICE40 frequency by using PLL yet?

Thank you for your help