Tim Newsome
Tim Newsome
Disabled in https://github.com/riscv/riscv-tests/commit/51ec34e28541f8c89cd89a6a9c137bd32ba71c29 to fix failure in https://github.com/riscv/riscv-tools/pull/236
Commit 22576f7c disabled the test coverage for the virtual priv register. These need to be re-enabled. I'm under the impression that it works, but if not then OpenOCD needs to...
https://github.com/riscv-software-src/riscv-config/blob/3f3a3b8a9c8fc88294ac5b4ac5c1ae9c92fa1305/riscv_config/isa_validator.py#L100
Beeman wrote (https://lists.riscv.org/g/tech-debug/message/1379): The icount trigger has a pending bit that is set on trigger match, and allows the action to be taken after an excursion to an inhibited privilege...
Function list: * read_abstract_arg * write_abstract_arg * sb_read_address * riscv013_read_debug_buffer Raised in #978
#485 introduces a list of tests that are known to cause an error on HiFive1. This issue is to go through that list, and fix the tests/infrastructure/whatever so that all...
## Location, date, and short issue description USA, Indiana state ## File timeseries.csv ## Issue details Case count hasn't changed in a couple of weeks. ## Snippet/screenshot ``` ... "Indiana,...
`c.ebreak` is a 16-bit breakpoint instruction, which is required to set breakpoints on 16-bit instructions. However, it is only defined as part of the C extension. That means that if...