Tim Newsome
Tim Newsome
#311 makes it so that we execute all the fences all the time, to cope with non-coherent multicore systems. Those should be the exception, though, and executing fences takes time....
This is verbose on ARM. http://openocd.org/doc/html/Server-Configuration.html says eg.: ``` > poll background polling: on target state: halted target halted in ARM state due to debug-request, \ current mode: Supervisor cpsr:...
It's not clear, as reported in #760.
Clarify this by explicitly saying the behavior only applies to running/halted harts respectively.
set_dmcontrol_hartsel() needs to ensure to write one of the actually selected harts to hartsello/hartselhi
Is there a set of regression tests that I can run with a single command somewhere? I'm modifying load_func() and store_func() and want to have some confidence that I didn't...
Use the `cease` instruction for this. It's unfortunately non-standard, but it does exist in Rocket so it's not crazy to use it here.
`disassemble` shows the whole function which is usually too much. Instead just show the nearest instructions for some context.
Used this test to confirm that https://github.com/riscv-software-src/riscv-isa-sim/pull/1013 works right.