Adjust send_opcode() timing to improve relibility of enable timing

[MarkGen]

When using a 93LC86C EEPROM the datasheet references critical timing of the start command.

"Note: When preparing to transmit an instruction, either the CLK or DI signal levels must be at a logic low as CS is toggled active high." send_opcode was modified by adding a HALF_CLOCK_PERIOD delay to ensure adequate time is provided for CLK signal to become low prior to raising CS & DI signals to HIGH.

Also added code to ensure CS,DI and CLK lines are brought LOW at start of function to ensure proper initialization if any of these lines were not returned LOW by another function or power glitch.

void MicrowireEEPROM::send_opcode(char op) { //------ //MG added to ensure CS & DI are low before //making them HIGH. digitalWrite(CS, LOW); digitalWrite(DI, LOW);

   //----------
  //MG - Commented out
    //digitalWrite(CLK, HIGH);
    //delayMicroseconds(HALF_CLOCK_PERIOD);
  //----------
    digitalWrite(CLK, LOW);
   delayMicroseconds(HALF_CLOCK_PERIOD); //MG added to
	//ensure adequate time for CLK to go LOW 
	//93LC86 Must have CS  & DI High on positive
	//edge of the clock bit which will happen in the transmit function
							
    digitalWrite(CS, HIGH);
    digitalWrite(DI, HIGH);
    // transmit start bit and two bit opcode
    transmit((1 << 2) | op, 3);

} 93LC86_EEPROM_Datasheet .pdf MicrowireEEPROM(cpp only).zip

[tim0s]

Thanks for the bug report! I didn't have problems when I tested the code, but your patch above looks good. If you can prepare a pull request I would be happy to accept it.