tillitis-key1
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tillitis
Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key 🔑
There are a few interesting linters, STAs that we could add to the CI flow to improve checks: Flawfinder https://dwheeler.com/flawfinder/ splint https://splint.org/ scan-build - exists as action in github https://clang-analyzer.llvm.org/scan-build.html...
It is quite possible that we could raise the clock frequency of the FPGA design. In order to do so we should analyze the timing after P&R and see what...
Some of the documentation under `docs` now lives in the Dev Handbook. Remove the probably outdated duplicates. - Note that `boards.md` and `fpga.md` are not in Dev Handbook and probably...
It is always good to get feedback from different tools. Other parsers, other synthesis, P&R tools. We haven't really done this. Lattice has the Diamond tools. We should push through...
Using the same device app for different client apps (with same or no USS) gives us the exact same CDI, often used as a secret key. In other cryptographic systems...
In the branch `uart_tx_debug_pin` is a proof of concept of a tx debug pin using GPIO4. The idea is to have a way of sending serial data that does not...
Note that I did have to investigate how `blake2s` in firmware works: I was looking for a way to hash multiple byte-arrays, which isn't possible now. The thing I run...
pynvcm is a hacky solution to write to the internal configuration memory NVCM in the Lattice FPGA we use. It's a bit hard to understand and a bit tricky to...
Use tkey-libs in firmware, too. This includes harmonizing the code and including the hardening stuff from the firmware in tkey-libs.
## Description This PR implements a change to the existing timer to add a free running mode. This is currently an initial version. The testbenches has not been updated with...