Theseus on `aarch64` - tracking issue

[NathanRoyer]

This is a tracking issue for the support of the aarch64/ARMv8 platform for Theseus.

bootstrap and basic initialization

• [x] nano_core as an UEFI application
• [x] log-compatible logger setup

memory management

• [x] Configuring the TCR register
• [x] porting the memory subsystem to aarch64 [WiP]
  • [x] memory_structs, frame_allocator, page_allocator: #693
  • [x] pte_flags: #699
  • [x] memory_aarch64, page_table_entry, memory: #701

interrupts

• [x] Installing handlers
• [x] Configuring GIC registers [WiP]
• [x] Configuring the DAIF register
• [x] porting Theseus' interrupt crates to aarch64
  • [x] irq_safety
  • [x] interrupts: #727
  • [x] architecture-independent interrupt handler: #972

task management

• [x] Pre-requisite: figure out how to get core ID for each CPU
• [x] context_switch_regular: #744
• [x] Basic Context type
• [x] Determine register to use for passing a new task's ID
  • see context_switch_regular::ContextRegular::set_first_register()
  • i.e., from setup_context_trampoline to task_wrapper
• [x] Configure aarch64 register used for Thread-Local storage
  • equivalent to FS_BASE and fs on x86_64; see Task::set_as_current_task()

SMP multicore support

• [x] Detecting secondary cores
• [x] Starting secondary cores at a controlled entry point
• [x] Obtain current CPU ID; see get_my_apic_id()
• [x] Configure paging / set up page tables for each CPU
• [x] Enable interrupts and set up interrupt handlers on each CPU
  • Theseus shares one page table and one IDT across all CPUs on x86_64; this should also work on aarch64

Basic I/O support for interactivity

• [x] Output over serial/UART
• [x] Input over serial/UART
• [x] Integration with device_manager and console
• [x] Move PL011 crate to the main workspace: #1040
• [x] Move interrupts::PL011_RX_SPI to the board config crate

Loading and Linking

• [x] Support aarch64 relocation types in write_relocation
  • Currently even the large code model on aarch64 does not generate branch instructions call/jump that can address the entire address space (as it does on x86_64).
  • [x] ~~Workaround: allocate pages for .text sections within a certain 128MiB range; see #970.~~
  • [x] Implement standard aarch64 relocation types for large code model and static relocations.
  • [x] Finish implementing overflow checks for relocations.

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Future endeavors

Once the above core subsystems and components are finished, we will open separate issues for the following:

• Supporting unwinding via aarch64-specific trampolines in unwind

• [x] Support basic PCI device discovery
  • [x] kernel/pci currently assumes an x86-style interface using Port I/O to access PCI config data, but aarch64 uses MMIO.
  • [ ] #1058

• More complex I/O, e.g., USB (?)
• Two-part abstraction of interrupt/CPU controllers:
  • per-CPU interrupt controller abstraction: enabling/disabling local timer interrupt, sending IPIs
  • system-wide interrupt controller abstraction: registering interrupt handlers, etc
• exceptions_full equivalent on aarch64