RandomX
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tevador
POWER support
Notably absent from the list of optimized architectures is any of the open ISAs. For integrity reasons it would make sense to support at least one of those ISAs in a proper mining role.
I propose the POWER ISA be used as reasonably powerful CPUs are commercially available that implement it.
Is there any interest in doing this and what would be needed to make it happen?
I'm actually much more interested in RISC-V than POWER. We'll see many RISC-V products in the coming years at very affordable prices. POWER CPUs are ridiculously expensive.
@SChernykh Both are open ISAs, but RISC-V is quite a bit behind POWER in performance and overall features IMO. POWER could be used as a reasonable miner right now, today, RISC-V not so much.
I think @nioroso-x3 was planning to implement a POWER JIT compiler (he already did hardware AES support for POWER7+).
In any case, the repository is open for PRs if you want to contribute. Refer to PR #125 to get an idea about the amount of code needed to integrate a new JIT compiler into RandomX.
@tevador thanks for that! I didn't want to duplicate effort, so if @nioroso-x3 is already working on support that's great. If for any reason that falls through, we may be able to take a look at a port.
Feel free to port the ARM jit, I'm currently too busy to look into it now. From what I see porting the ARM code will be easy, the only difference would be the stack register that's usually r2 in ppc.
Hi @tevador @madscientist159 there seems to be cmake support for this repo to be compiled on ppc64le. But, however it is missing native JIT from what i can gather. Is that the only missing piece for getting a native ppc64le performance?.
Thanks.
Hi @tevador @madscientist159 there seems to be cmake support for this repo to be compiled on ppc64le. But, however it is missing native JIT from what i can gather. Is that the only missing piece for getting a native ppc64le performance?.
@supr As I understand it, JIT is the main thing that's needed for ppc64le. Some additional speedup might be possible on POWER9 by using the VAS/NX AES coprocessor, but that can't be done until Linux implements userspace support for it.
Is this the asked VAS/NX Part we need?
https://lwn.net/Articles/807536/
@sammy2k8-lab The AES acceleration is built in to the POWER ISA, as part of each core, just like x86. All you need to do is use the AES instructions for POWER instead of the AES instructions for x86...
Side note, if there's enough interest in this overall to offer a bounty, things might get ported a lot faster...
Support for POWER AES instructions is already in the source, has been for years. https://github.com/tevador/RandomX/pull/41
@madscientist159 I am currently (trying) to port the jit to ppc64le (POWER ISA v 3.0c). I am using this project to learn assembly (and C/C++) so i cannot guarantee that it will succeed. I am using the a64 jit as the primary reference because i learned that i hate the x86_64 ISA and i do not fully understand the jit code, the asm includes and in general how it works ^^"
Yeah, if there was a bounty things may go faster! A bounty for RISC-V would be fine too.