Output signal is too long and out of spec

[Sojourneer]

The output signal's bit length for WS2811 is 1.25uS in high speed mode, but the FTDI is putting out 1.5uS as shown on a logic analyzer. The allowable jitter is 75nS (150nS?) according to the WS2811 data sheet, so this is out of spec. The problem seems to be due to the SPI CLK signal adding its duration to the data bit length.

BTW, thanks for this library. It is the only FTDI code I could get to work (with the caveat above) for my WS2811 experiments.