hoodlum

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FPGA world suffers a lot from fragmentation - some tools produce Verilog, some VHDL, some - only subsets of them, creating low-level LLVM-like alternative will help everyone, so HDL implementations...

XVilka

Keywords "def" and "def mut"

1

This issue is for bikeshedding keywords. "def" is introduced as an analog for "wire" in Verilog, albeit more strictly typed (no latches should be inferred when using this). The term...

tcr

Undeclared `_FSM` reg breaks `sequence`

2

With the `sequence.hdl` example, the `_FSM` variable in the generated Verilog is never declared, so it defaults to a 1-bit `wire`. This results in it toggling between two states instead...

kevinmehall

tcr

Testing and verification is the part of Verilog I'm weakest at. What should it look like if it were redesigned and implemented in Hoodlum?

tcr

This will allow the ethernet.hdl hack naming `__FSM_1` to be removed.

tcr

Currently, you can specify a unfixed width literal with a leading 0: ``` 115 => 115 0d115 => 115 0b1110011 => 115 0x73 => 115 ``` You can specify a...

tcr

tcr

tcr

In an on { } statement.

tcr