Implement RV32C

[takahirox]

[takahirox]

It would be something like this

1. Fetch instruction 32-bit
2. Check the first 16-bits if it's compressed instruction
3. Decompress if the instruction is compressed
4. Increment PC depends on whether the instruction is compressed, 2 for compressed instruction and 4 for non-compressed one

or

1. Fetch instruction 16-bit
2. Check if it's compressed instruction
3. Decompress if the instruction is compressed, or fetch the following 16-bit if it isn't compressed
4. Increment PC depends on whether the instruction is compressed, 2 for compressed instruction and 4 for non-compressed one

And the current implementation expects fixed 32-bit instruction length at some places. We need to update them.

The biggest problem is riscv-tests doesn't seem to have tests for each C instruction. (Or can I compile rv32/64u* tests with compressed instructions by adding -march compile/assemble options? If I can't, contributing to tests would be nice.)

[takahirox]

Regarding the test, I succeeded in building riscv-tests with compressed instructions by replacing -march=rv32/64g with -march=rv32/64gc in isa/Makefile.

[takahirox]

I've reviewed riscv-tests and think the existing rv32/64uc-p-rvc may be good enough now.

[takahirox]

Done RV64C. RV32C is not yet.