Aboobacker MK
Aboobacker MK
@philipabbey Project maintainer here, We are sorry for the frustrating experience. As we noted in the user interface, Verilog is a n experimental feature, it is neither feature complete nor...
@092vk Yes, but this is something we can do in the future, That is why we kept this issue open
Timezone information is important as we are not showing the time based on user's time zone yet. So showing IST time without specifying IST mark will be misleading
We need to allow students to set their timezone
Yes, but we need to merge with similar issues and make detailed one
The gradient looks bit off as we don't use gradients in any other part of the platform
UI for the sign in model looks weird, use the same UI/UX pattern, do not introduce new colours or other UI elements
This requires training a model with our circuit data structure, it will being additional complexity and infrastructure expenses. But if you want to build as a third party integration using...
This seems an overkill at this point, we can revisit this in future if we allow customisations on pagination.
@yaxit24 Update PR title to a meaningful one. Also make description more concise, current one looks like a jargon generated by the LLM