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board/system76/common: use SLP_S0# pin for modern standby detection
Previously, CPU_C10_GATE# was used for detecting entry into s0ix / Modern Standby.
Intel documentation says that SLP_S0# should be used for s0ix detection instead, and CPU_C10_GATE# is intended for VCCSTG power gating, so switch the pin to improve s0ix detection reliability.
Fixes https://github.com/system76/firmware-open/issues/199
Tested on Clevo NS51MU, firmware built for system76/darp7
.
References:
- Intel docs #575570 rev 0.5, #607872 rev 2.2
- Chromium EC: https://chromium.googlesource.com/chromiumos/platform/ec/+/master/power/intel_x86.c#41
Signed-off-by: Michał Kopeć [email protected]
Verified behavior on lemp10.
Should be tested on:
- All TGL-U boards
- Any 1 TGL-H board
- lemp11
- Any 1 other ADL board
Test with/after https://github.com/system76/firmware-open/pull/341 for updated coreboot base.
gaze17 and oryp9 do not connect SLP_S0#
to the EC, but we use S0ix on them because of problems with S3.
Ah, I don't have access to these models' schematics so I didn't realize they didn't have SLP_S0#
connected to the EC. Does it make sense to implement a function like is_suspended
that does the right check for boards with SLP_S0#
, CPU_C10_GATE#
only, or with S3 enabled?
Can probably just define SLP_S0_N
as the CPU_C10_GATE_N
pin for those 2 in their gpio.c
with a FIXME
.
For some reason, this change on Lemp11 is causing a failure to post on only the integrated ram.
Merged with #298.