snippy
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Reproduce on 1.0 snippy command line: ``` ./llvm-snippy -march=riscv64-linux-gnu -mattr="+f,+d" -reserved-regs-list="F0_D,F1_D,F2_D,F3_D,F4_D,F5_D,F6_D,F7_D,F8_D,F9_D,F13_D,F14_D,F15_D,F16_D,F17_D,F18_D,F19_D,F20_D,F21_D,F22_D,F23_D,F24_D,F25_D,F26_D,F27_D,F28_D,F29_D,F30_D,F31_D,X3,X4" -num-instrs=1000 -seed=0 -model-plugin=None ./layout-stack.yaml --init-regs-in-elf -last-instr=RET --honor-target-abi --external-stack ``` where layout-stack.yaml looks like: ``` sections: - no: 0 VMA:...
Reproduced on 1.0 layout.yaml: ```yaml options: march: riscv64 model-plugin: None seed: 0 dump-initial-registers-yaml: regs.yaml sections: - name: text VMA: 0x1000 LMA: 0x1000 SIZE: 0x1000 ACCESS: rx - name: data VMA:...
Reproduced on 1.0 I want just to generate a simple snippet and link it with a simple wrapper. To do this I created config file: ```yaml options: march: riscv64 model-plugin:...
Reproduce on 1.0 layout.yaml: ```yaml options: march: riscv64 mabi: lp64d model-plugin: None seed: 0 sections: - name: text VMA: 0x1000 LMA: 0x1000 SIZE: 0x1000 ACCESS: rx - name: data VMA:...
Reproduced on 1.0 layout.yaml: ```yaml options: march: riscv64 sections: - name: text VMA: 0x1000 LMA: 0x1000 SIZE: 0x1000 ACCESS: rx histogram: - [ADD, 1] ``` Command: ```sh llvm-snippy layout.yaml ```...
Reproduced on 1.0 I can't understand why default architecture is host even if it isn't supported. Can you please implement that default architecture is host if host architecture is supported,...
Reproduced on 1.0 There is no model that is provided with snippy but generation with the simplest layout would fail due to fail to find `libRISCVModel.so`. layout.yaml: ```yaml options: march:...
Reproduced on 1.0 Snippy `-march` option is actually target triple. According to [RISC-V toolchain convention](https://github.com/riscv-non-isa/riscv-toolchain-conventions) `-march=rv64gc` must be ok, but in snippy to specify rv64gc I need to set `-march=riscv64`...
Message about starting the simulation "#===Simulation Start===" made longer. This will allow for a clearer separation of the snippy output at generation time from the model output at run time.
Hello! I think the message about starting the simulation "#===Simulation Start===" is too short. The simulation trace is often long lines, so I think it's better for this log to...