sy2002

@mrjoso This core attempts to fix the problem and therefore should be able to support the IDE64 cartridge: [c64mega65v52a2e2.zip](https://github.com/user-attachments/files/19521830/c64mega65v52a2e2.zip)

@xlar54 Thank you for testing - I highly appreciate your support. @Kugelblitz360 Thank you for the clarity - super valuable insight. Then this whole thing is not the kind of...

@mrjoso and @Kugelblitz360 Thank you both for your support. Since I don't have an IDE64 handy I need your help to debug this: Does any one of you have a...

@mrjoso And here are some additional thoughts that came up when I asked chatGPT for myself :-) Besides a lot of ["irrelevant stuff" that it output](https://chatgpt.com/share/67f37da8-5700-8001-b611-4f67d1f759a4), here are some relevant...

@mrjoso Thank you for your support! Happy to do a Zoom call or something like this, to stare at the code together and to brainstorm together, if you want to....

@mrjoso thank you for starting to looking into this. If you want to check, if the version of `fpga64_buslogic.vhd` you looked at is correct, then use the branch `dev-fix-pla` because...

@mrjoso Any appetite for doing some ILA debugging here? I am sure I made some stupid mistake - or we have one of these pesky "+/- 1 or 2" clock...

@mrjoso Scratch my last comment. My new friend and coding assistant chatGPT helped me in debugging this and it found something that might have been the reason that even though...

@mrjoso Thank you for testing and for your analysis. The regression is odd, I need to look deeper. Looking at the code snippets you posted in the comment, I cannot...

@mrjoso So I found the reason why we had the regression: Since I refactored the wrapper and also the signalling of the Ultimax unmapped mode in 5.2A2E3 compared to 5.2A2E2,...