Simulation: Timer Interrupt Hardware: Test Daisy Chaining Edge Case

[sy2002]

Enhance the simulation testbench of the timer interrupt hardware, including dev_int.asm , so that the following daisy chaining edge case is tested:

Timer1 fires. Timer0 fires one (or very little) cycle(s) after timer1.

Expected behaviour: Timer1 is allowed to execute its interrupt. After that, timer0 executes its interrupt.

[sy2002]

This activity is part of issue #45

[sy2002]

Moved from V1.6 to V1.7 because all tests so far indicate that the interrupt system in general and the timer interrupt in particular are both reasonably stable: Everything seems to work great, and apart from the known nasty bug in issue #62 which is not a real-life application/situation and not easy reproduce, this is absolutely good enough to release.