cnn_hardware_acclerator_for_fpga
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This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs
I would like to ask if there is any documentation - paper in which your convolver architecture was based.
Hi. The module for c_shift_ram_0 is not present in the repository. It will be really helpful if you can provide with the code or maybe the logic behind how it...
Hey, what should the ip_data.txt look like? Are the values in int format?