on 'Floating_Point_IEEE_754_Multiplication'

[zehonyi21]

Hi, I was checking the verilog code of 'Floating_Point_IEEE_754_Multiplication' and I think it needs some upgrade.

1. When we assign 'zero', where the line is

assign zero = exception ? 1'b0 : (product_mantissa == 23'd0) ? 1'b1 : 1'b0;

I think it also needs to consider whether one of exponents of input has all zero thereby it checks 'true' zero. Thus the code should be like

assign zero = exception ? 1'b0 : (product_mantissa == 23'd0) & !((|a[30:23]) & (|b[30:23]))? // zero mantissa and zero exponent -> true zero 1'b1 : 1'b0; // Nested conditions for finding 0 expression of FP32

2. When we assign 'exponent', where the line is

assign exponent = sum_exponent - 8'd127 + normalised;

I think we need to consider underflow of exponent since we subtract by 127 which is quite huge value. Thus the code should be like

assign exponent = (sum_exponent[8] | sum_exponent[7]) ? // sum_exponent[7] -> 128 sum_exponent - 8'd127 + normalised : 9'd0;

3. When we check the calculation by using 'iteration', where the line is

iteration (32'hC152_6666,32'h0000_0000,1'b0,1'b0,1'b0,32'h441E_5375,`LINE); //-13.15 * 0 = 0;

I think the expected value(here it is 32'h441E_5375) should be zero by comment(//-13.15 * 0 = 0;). Thus the code should be like

iteration(32'hC152_6666,
            32'h0000_0000,
            1'b0,
            1'b0,
            1'b0,
            32'h8000_0000,  // -0
            `__LINE__);
// -13.15 * 0 = 0

Thank you for reading my issue and I would be glad if you give me any feedback.