Victor Suarez Rovere
Victor Suarez Rovere
I find this code to program Spartan6 devices useful. It's based on OpenOCD, and it works. Can be added here: https://github.com/enjoy-digital/litex/blob/master/litex/build/xilinx/programmer.py Any interest? ``` # Copyright (C) 2024 Victor Suarez...
In current state, nextpnr-xilinx reports this error when trying to use clocked DSPs: `ERROR: Clocked DSP48E1s are currently unsupported` The way to mitigate it is by adding this command to...
With some glue I wrote for cores from others I was able to show the LiteX boot console on a LCD with a 8080 bus. Since it doesn't need changes...
I successfuly integrated a somewhat old core from @xobs into a newer version of LiteX, it works well, so support for SPI PSRAM could be mainstreamed, #https://github.com/suarezvictor/micropython/commit/d7d2203cab9c2909395bbb5a9cff3d5016fa81a3#diff-f689a3f83aaaa1076106b25044284fc4d4c04e2cd3e173ef6a9d9e74e6840348R79 EDIT: this may...
Combining the following developments it should be possible to develop a framebuffer backed on PSRAM: https://github.com/enjoy-digital/litex/issues/1619 https://github.com/enjoy-digital/litex/issues/1618 So far the terminal works: 
When I translate some code to Verilog, there are some "do nothing" states that consumes a clock cycle where that can be avoided. For example, the only thing that state...
generate verilog files for various configurations (simulation, RMII, axi-lite/wishbone), plus etherbone **NOTE: not working yet**
It seems that in a foor loop, amount of stages for each iteration ca be fractional, it would be good to force at least one for iteration ``` for (i=0;...
Here is some info for any plan to do the port to such device. The FPGA is also a Spartan 6 https://sigrok.org/wiki/Digilent_Analog_Discovery/Info Any hint on how to discover the FTDI...
I'm doing some power measurements using the internal anergy meters of the CPU, using MSR registers. I think that would do more accurate measurements for PC's CPUs. I'm open to...