Victor Suarez Rovere
Victor Suarez Rovere
When yosys is called with DSP enabled for xilinx target, nextpnr-xilinx gives this error: `ERROR: Clocked DSP48E1s are currently unsupported` Solution: add -nodsp option in https://github.com/enjoy-digital/litex/blob/master/litex/build/xilinx/yosys_nextpnr.py#L166 `'yosys -p "synth_xilinx -flatten...
When using nextpnr+xilinx, ODDR instances for VideoGenericPHY keeps being generated even when SDROutput is requested a temporary solution found was to replace the SDROutput with direct assignment (in https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/video.py#L700) ```...
Is there any "hello world" example of partial reconfiguration / ICAP use? LiteX has a core for that (https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/icap.py) but I'd would be interested on any real use of it,...
hi! I friend of mine challenged me saying that if LiteX/nMigen makes things so easy, I should be show him an example of a led blink project in less than...
License
Hi, I'm interested in this library but license isn't clear Maybe it can be included in sources or at least in a separare LICENSE file
I think this idea could be of value: Let's assume a database is created from a bitstream generated by the vendor toolchain using fuzzers Then, a similar alternative database is...
for variables declared as const, never generate registers for the pipeline (just wires) This will ease the job of the synth tool and be easier than tracking if the variables...
avoiding the big hiearchy so less pressure on ghdl plugin
Binary to decimal can be executed in a single cycle using few resources with this algorithm https://jk-jeon.github.io/posts/2022/02/jeaiii-algorithm/
I had to do some tweaks to install the open-source toolchain for the Arty board that I'd like to share, and hopefully the [wiki](https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/TUTORIALS/toolchain_arty.md) can be updated $PRJXRAY and $LEARN_FPGA...