Victor Suarez Rovere

Good! I'm impressed about how fast you made the fix. I'm eager to try it with other cores I have

My example works too. Kudos to Sylvian! There's still room for optimization as I posted in the related issue https://github.com/sylefeb/Silice/issues/248. I'm not familiar with the code to send patches but...

I think a good way to save many cycles is as follows. In the following code, there are many `else` blocks that the only thing they do is to set...

I think you have a dilemma between keeping backwards compatibility, and offering a way of producing faster code. Why not both? You may pass a flag for retro compatibility (like...

I was thinking a bit about this and I think the example construct with and without 'break' (see below) should produce the exact same results, as users would expect, and...

In my view, the code duplication should be possible, maybe depending on optimization level. There are situations where the code block will just set a flag, and the synth tool...

It's is clear for anyone that too much optimization could be dangerous, but to implement for example the UART core, I'd be willing to set optimization level to the sky...

This is a matter of personal taste, but I'd prefer a dangerous optimization flag, than code that's hard to follow and understand I really think the 'break' version and the...

This is great news and to me the best that can be done is to add options for optimization levels. If they can be passed by command line, it would...

I like the idea of a language extension and that kind of overriding. Happy of being part of this design changes!