Misleading SPI to GPIO pin mapping in code documentation: CE0 should be mapped to GPIO 8

[ghen]

https://github.com/stianeikeland/go-rpio/blob/d8d85b35367c123e3bd3cb16c7fe0aa1f50bb19f/spi.go#L27-L30

According to the official hardware documentation, SPI0 CE0 is mapped to GPIO 8. Tested with actual hardware (Raspberry Pi4).

https://www.raspberrypi.com/documentation/computers/raspberry-pi.html

[ghen]

Proposed fix:

From 6afca753a6d7bc38cbf61c498603e10154609386 Mon Sep 17 00:00:00 2001
From: Eugene Y <[email protected]>
Date: Tue, 16 Jan 2024 20:06:03 +0300
Subject: [PATCH] fix: SPI0 CE0 is mapped to RPI GPIO8

Signed-off-by: Eugene Y <[email protected]>
---
 spi.go | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/spi.go b/spi.go
index 7a5954e..c39288a 100644
--- a/spi.go
+++ b/spi.go
@@ -26,7 +26,7 @@ var (
 
 // SpiBegin: Sets all pins of given SPI device to SPI mode
 //  dev\pin | CE0 | CE1 | CE2 | SCLK | MOSI | MISO |
-//  Spi0    |   7 |   8 |   - |    9 |   10 |   11 |
+//  Spi0    |   8 |   7 |   - |    9 |   10 |   11 |
 //  Spi1    |  16 |  17 |  18 |   19 |   20 |   21 |
 //  Spi2    |  40 |  41 |  42 |   43 |   44 |   45 |
 //
@@ -182,7 +182,7 @@ func clearSpiTxRxFifo() {
 func getSpiPins(dev SpiDev) []Pin {
 	switch dev {
 	case Spi0:
-		return []Pin{7, 8, 9, 10, 11}
+		return []Pin{8, 7, 9, 10, 11}
 		// ommit 35, 36, 37, 38, 39 - only one set of SPI0 can be set in Spi mode at a time
 	case Spi1:
 		return []Pin{16, 17, 18, 19, 20, 21}
-- 
2.34.1