Baruch Sterin

Provide a way to set environment variables when using cmake-presets

8

For example, a preset that uses `vcpkg` requires a path to `vcpkg.cmake`, whose location may vary across machines. As the [documentation ](https://github.com/microsoft/vscode-cmake-tools/blob/develop/docs/cmake-presets.md#vcpkg-integration)suggests, this can be done by using `$env{VCPKG_ROOT}`. Using...

The example ignores the `ready` signal on the output side. `expectDequeueSeq` fails to catch the problem because it consumes the data as soon as it is available. It tests the...

[FIRRTL] Add lowering option to inline memory wrapper modules (#5681)

8

This PR addresses issue #5681. When the new `inlineMemoryWrapperModules` is enabled, at the end HWMemSimImpl pass, it inlines the newly created memory wrapper modules and then removes them. Input FIRRTL...

For details see issue #5066

Support nested SytemVerilog interface as a port connection in a module

1

First, an internal error is reported when a nested interface is used as a module port connection. The following code ```SystemVerilog interface A; logic x; endinterface interface B; A a();...

Spurious combinational loop warning depending on the name of formal parameter of an empty task

1

This isssue is somewhat weirder than the previous ones. The following example ```systemverilog interface I; logic foo; endinterface module M0; logic foo; initial begin foo = 1; end I C();...

C++ compilation error when calling a class member accepting a virtual interface with a wrong interface type

1

Calling an class member accepting a virtual interface with the wrong interface type, results in C++ compliation error. Here, an interface of type `I1` is provided as a parameter to...

Bad C++ generated with interface array element being assigned to a virtual interface

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This issue is probably a duplicate of #5270. However, it does not produce an internal error. Instead, it genertes C++ code that does not compile. At this point any attempt...

Internal error when assigning a member of an interface array to a virtual interface

1

Assigining a member of an interface array to a virtual interface results in an internal error: ```systemverilog interface A; endinterface module top; A a[2](); initial begin virtual A aa =...