Baruch Sterin

The `environment` keyword is used to set environment variables set by the preset to `CMakeLists.txt`. I would like a way to set the content of the environment passed to the...

Yes, this can be done this way, but I don't think it's a good idea in this scenario. The file `CMakePresets.json` is usually source controlled. In my example it describes...

It is definitely possible to this. It is also possible to use a symbolic link to point to the vcpkg installation. I just think this overcomplicates things. While `CMakePresets.json` is...

Hi, I've also noticed the problem. Here's a simple test using ChiselTest: ```scala class FifoSpec extends BaseSpec { "RegFIFO" in { test(new RegFifo(UInt(16.W), 16)) { dut => { // First...

Thanks! I've rebased the pull request branch and implemented the above changes. It is now an option --inline-mem. > Thanks! I think the option makes sense. One question I have...

I've noticed another problem with the pull request. The pass ends up with a verification failure when there's a `firrtl.annotations.LoadMemoryAnnotation` affecting the memory. I'll investigate a bit.

Not yet, no. It had problems multiple memories per module, and with out-of-line file initialization of memories. Multiple memories is easily solved, but out-of-line file initialization is complicated to handle...

While testing I've discovered a few more problems: This latest commit resolves the following problems: * Multiple memories in the same module did not work because inner symbols created for...

@seldridge Could you review the latest commits?

Vivado does not infer BRAMs from this Verilog style, even though register reads and writes are all mutually exclusive. Vivado is very picky about the style of Verilog it is...