spatial-lang

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Initially this can be round robin allocation, which is probably good enough for apps with many load/store channels In the future partitioning of data structures can also be implemented

shadjis

If you parallelize an unaligned load, you could potentially get the wrong result in the app since the Linebuffer assumes a constant enqueue stride and therefore has one wren signal....

mattfel1

The bug where it takes two reads to actually get the data from a register over AXI.. I tried delaying the axi_rvalid signal inside of the AXI4LitetoRFBridge verilog but I...

mattfel1

Example: From Sort_Radix, this can be merged to be a single store node ``` if (valid_buffer == a) { // println("dumping buf a") data_dram store a_sram } else { //...

mattfel1

Use MACC IP

3

Rather than use separate DSP blocks for multiplies and then adds, the Xilinx MACC IP can be used. This would reduce DSP utilization.

shadjis

URAMs are 72 bits wide, which means that 2 32-bit words can fit in each entry (or 4 16-bit words, etc.) This can be done in the case of sequential...

shadjis

Remove Potentially Unnecessary Pipe from alignedStore

2

Because fringe backpressure should be good for cmdStream now

mattfel1

Initiation interval calculation problems

2

Using this issue to track all initiation interval calculation issues - [ ] #151 - Should depend on length between read and write, e.g. s(i) = f( s(i - 1)...

dkoeplin

Use URAMs on F1

6

The F1 has UltraRAMs which can be used for larger SRAMs. However, SRAMs need to be explicitly assigned to URAMs using the following syntax: `(* ram_style = "ultra" *) reg...

shadjis

AccessDispatch has more than one dispatch

2

Stefan found this in vgg_1d, pasted below. I think this is a bug, unless if there is something logical I should do when dispatched to multiple duplicates? Issue is on...

mattfel1