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srsran
srsran
Configuration of external clock with srsRAN
I have a setup with the following hardware:
- Ettus Research X310
- Ettus Research CDA-2990 (The Clock)
- Dell Precision 3660 with 13900K
I want the X310 to use the external clock. While I have srsRAN start up correctly with my configuration, I am not really sure if the clock is being used correctly. The X310 is connected via PCIe to the Dell Workstation PC. The Clock is connected like so to the SDR:
- Clock:
10MHz Out--> X310:Ref In - Clock:
PPS Out--> X310:PPS Trig In
And also, the Clock has a GPS antenna connected to the GPS ANT Input port.
So, as far as I know, everything should be connected correctly.
I am using the following configuration with srsRAN:
mf:
addr: 127.0.0.5 # The address or hostname of the AMF.
bind_addr: 127.0.0.1 # A local IP that the gNB binds to for traffic from the AMF.
ru_sdr:
device_driver: uhd # The RF driver name.
device_args: type=x300 # Optionally pass arguments to the selected RF driver.
clock: external
sync: external
clock_ppm: 0
freq_offset: 0
lo_offset: 0
srate: 184.32 # RF sample rate might need to be adjusted according to selected bandwidth.
tx_gain: 30 # Transmit gain of the RF might need to adjusted to the given situation.
rx_gain: 26 # Receive gain of the RF might need to adjusted to the given situation.
time_alignment_calibration: auto
cell_cfg:
dl_arfcn: 650000 # ARFCN of the downlink carrier (center frequency).
band: 78 # The NR band.
channel_bandwidth_MHz: 100 # Bandwith in MHz. Number of PRBs will be automatically derived.
common_scs: 30 # Subcarrier spacing in kHz used for data.
plmn: "99970" # PLMN broadcasted by the gNB.
tac: 7 # Tracking area code (needs to match the core configuration).
pci: 1 # Physical cell ID.
log:
filename: /tmp/gnb.log # Path of the log file.
all_level: debug # Logging level applied to all layers.
pcap:
mac_enable: false # Set to true to enable MAC-layer PCAPs.
mac_filename: /tmp/gnb_mac.pcap # Path where the MAC PCAP is stored.
ngap_enable: false # Set to true to enable NGAP PCAPs.
ngap_filename: /tmp/gnb_ngap.pcap # Path where the NGAP PCAP is stored.
Starting srsRAN shows the following debug log:
srs@ws1:~/srsRAN_Project/build86ed/apps/gnb$ sudo ./gnb -c n78_siso_100mhz.yml
Lower PHY in quad executor mode.
--== srsRAN gNB (commit 5e6f50a20) ==--
Connecting to AMF on 127.0.0.5:38412
Available radio types: uhd.
[INFO] [UHD] linux; GNU C++ version 11.3.0; Boost_107400; UHD_4.4.0.0-0ubuntu1~jammy1
[INFO] [LOGGING] Fastpath logging disabled at runtime.
Making USRP object with args 'type=x300,master_clock_rate=184.32e6,send_frame_size=8000,recv_frame_size=8000'
[DEBUG] [NIRIO] rpc_client stopping...
[DEBUG] [NIRIO] rpc_client stopped.
[DEBUG] [NIRIO] rpc_client stopping...
[DEBUG] [NIRIO] rpc_client stopped.
[INFO] [X300] X300 initialization sequence...
[DEBUG] [X300] Motherboard 0 has remote device ID: 1
[DEBUG] [X300] Setting up basic communication...
[INFO] [X300] Connecting to niusrpriorpc at localhost:5444...
[DEBUG] [NIRIO] rpc_client stopping...
[DEBUG] [NIRIO] rpc_client stopped.
[INFO] [X300] Using LVBITX bitfile /usr/share/uhd/images/usrp_x310_fpga_HG.lvbitx
[DEBUG] [NIRIO] rpc_client stopping...
[DEBUG] [NIRIO] rpc_client stopped.
[DEBUG] [X300] Using FPGA version: 39.1 git hash: 92c09f7
[DEBUG] [X300] Loading values from EEPROM...
[DEBUG] [X300] Setting up RF frontend clocking...
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=8, Requested=0.000000, Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=4, Requested=0.000000, Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=5, Requested=0.000000, Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=0, Requested=0.000000, Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[DEBUG] [X300] x300_clock_ctrl::set_clock_delay: Which=2, Requested=0.000000, Digital Taps=5, Half Shift=OFF, Analog Delay=0 (OFF), Coerced Delay=0.000000ns
[INFO] [GPS] Found an internal GPSDO: LC_XO, Firmware Rev 0.932
[INFO] [X300] Radio 1x clock: 184.32 MHz
[DEBUG] [X300] Motherboard 0 has local device IDs:
[DEBUG] [X300] * 2
[DEBUG] [X300] Assigning DMA channel 0 to remote EPID 0
[DEBUG] [NIRIO] NI-RIO RX FIFO Transfer Check Quirk Enabled.
[DEBUG] [RFNOC::MGMT] Starting topology discovery from device[local]:2/sep:1
[DEBUG] [RFNOC::MGMT] Discovered node device:1/xport:0
[DEBUG] [RFNOC::MGMT] Initialized node device:1/xport:0
[DEBUG] [RFNOC::MGMT] Discovered node device:1/xbar:0
[DEBUG] [RFNOC::MGMT] Initialized node device:1/xbar:0
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:0
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:0
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:1
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:1
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:2
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:2
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:3
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:3
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:4
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:4
[DEBUG] [RFNOC::MGMT] Discovered node device:1/sep:5
[DEBUG] [RFNOC::MGMT] Initialized node device:1/sep:5
[DEBUG] [RFNOC::MGMT] The following endpoints are reachable from device[local]:2/sep:1
[DEBUG] [RFNOC::MGMT] * 1:0
[DEBUG] [RFNOC::MGMT] * 1:1
[DEBUG] [RFNOC::MGMT] * 1:2
[DEBUG] [RFNOC::MGMT] * 1:3
[DEBUG] [RFNOC::MGMT] * 1:4
[DEBUG] [RFNOC::MGMT] * 1:5
[DEBUG] [RFNOC::LSM] Adding node device:1/xport:1 to topology graph outside of discovery.
[DEBUG] [RFNOC::LSM] Adding transport adapter on xbar port 1
[DEBUG] [RFNOC::GRAPH] Connecting the Host to Endpoint 1:0 through Adapter 0 (0 = no preference)...
[DEBUG] [RFNOC::MGMT] Bound stream endpoint with Addr=(1,0) to EPID=2
[DEBUG] [RFNOC] Started thread uhd_ctrl_ep0001 to process messages control messages on EPID 1
[DEBUG] [RFNOC::MGMT] Established a route from EPID=1 (SW) to EPID=2
[DEBUG] [RFNOC] Created ctrlport endpoint for port 0 on EPID 1
[DEBUG] [RFNOC::GRAPH] Connection to Endpoint 1:0 completed through Device 2. Using EPIDs 1 -> 2.
[DEBUG] [RFNOC] Created ctrlport endpoint for port 2 on EPID 1
[DEBUG] [0/DUC#0] Checking compat number for FPGA component `0/DUC#0': Expecting 0.1, actual: 0.1.
[DEBUG] [0/DUC#0] Loading DUC with 3 halfbands and max CIC interpolation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DUC#0 (NOC ID=d0c00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 3 on EPID 1
[DEBUG] [0/DDC#0] Checking compat number for FPGA component `0/DDC#0': Expecting 0.1, actual: 0.1.
[DEBUG] [0/DDC#0] Loading DDC with 3 halfbands and max CIC decimation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DDC#0 (NOC ID=ddc00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 4 on EPID 1
[DEBUG] [0/Radio#0] Checking compat number for FPGA component `0/Radio#0': Expecting 0.1, actual: 0.1.
[DEBUG] [0/Radio#0] ADC capture delay self-cal done (Tap=14, Window=25, TapDelay=78.125ps, Iter=1)
[DEBUG] [0/Radio#0] Actual sample rate: 184.32 Msps.
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Radio#0 (NOC ID=12ad1000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 5 on EPID 1
[DEBUG] [0/DUC#1] Checking compat number for FPGA component `0/DUC#1': Expecting 0.1, actual: 0.1.
[DEBUG] [0/DUC#1] Loading DUC with 3 halfbands and max CIC interpolation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DUC#1 (NOC ID=d0c00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 6 on EPID 1
[DEBUG] [0/DDC#1] Checking compat number for FPGA component `0/DDC#1': Expecting 0.1, actual: 0.1.
[DEBUG] [0/DDC#1] Loading DDC with 3 halfbands and max CIC decimation 255
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/DDC#1 (NOC ID=ddc00000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 7 on EPID 1
[DEBUG] [0/Radio#1] Checking compat number for FPGA component `0/Radio#1': Expecting 0.1, actual: 0.1.
[DEBUG] [0/Radio#1] ADC capture delay self-cal done (Tap=20, Window=22, TapDelay=78.125ps, Iter=1)
[DEBUG] [0/Radio#1] Actual sample rate: 184.32 Msps.
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Radio#1 (NOC ID=12ad1000)
[DEBUG] [RFNOC] Created ctrlport endpoint for port 8 on EPID 1
[DEBUG] [0/Replay#0] Checking compat number for FPGA component `0/Replay#0': Expecting 1.1, actual: 1.1.
[DEBUG] [RFNOC::BLOCK_CONTAINER] Registering block: 0/Replay#0 (NOC ID=4e91a000)
[DEBUG] [0/DDC#1] Not setting frequency until sampling rate is set.
[DEBUG] [0/DDC#1] Not setting frequency until sampling rate is set.
[DEBUG] [0/DUC#1] Not setting frequency until sampling rate is set.
[DEBUG] [0/DDC#0] Not setting frequency until sampling rate is set.
[DEBUG] [0/DDC#0] Not setting frequency until sampling rate is set.
[DEBUG] [0/DUC#0] Not setting frequency until sampling rate is set.
[DEBUG] [0/Radio#0] Running ADC self-cal...
[DEBUG] [0/Radio#1] Running ADC self-cal...
[DEBUG] [CONVERT] get_converter: For converter ID: conversion ID
Input format: fc32
Num inputs: 1
Output format: sc16_chdr
Num outputs: 1
Using best available prio: 3
[DEBUG] [X300] Assigning DMA channel 1 to remote EPID 2
[DEBUG] [RFNOC::MGMT] Established a route from EPID=3 (SW) to EPID=2
[DEBUG] [RFNOC::MGMT] Established a route from EPID=3 (SW) to EPID=2
[DEBUG] [RFNOC::MGMT] Finished TX stream setup for EPID=2
[DEBUG] [MULTI_USRP] Inconsistent TX rates when creating streamer! Harmonizing to 1.8432e+08
[WARNING] [0/Radio#0] Attempting to set tick rate to 0. Skipping.
[DEBUG] [CONVERT] get_converter: For converter ID: conversion ID
Input format: sc16_chdr
Num inputs: 1
Output format: fc32
Num outputs: 1
Using best available prio: 3
[DEBUG] [X300] Assigning DMA channel 2 to remote EPID 2
[DEBUG] [RFNOC::MGMT] Established a route from EPID=4 (SW) to EPID=2
[DEBUG] [RFNOC::MGMT] Initiated RX stream setup for EPID=2
[DEBUG] [RFNOC::MGMT] Finished RX stream setup for EPID=2
[DEBUG] [0/Radio#0] spp value 2044 exceeds MTU of 4096! Coercing to 1020
Cell pci=1, bw=100 MHz, dl_arfcn=650000 (n78), dl_freq=3750.0 MHz, dl_ssb_arfcn=647328, ul_freq=3750.0 MHz
==== gNodeB started ===
Type <t> to view trace
^CStopping ..
[DEBUG] [0/Replay#0] deinit() called, but not implemented.
[DEBUG] [0/Replay#0] Invalidating register interface
[DEBUG] [0/DDC#1] deinit() called, but not implemented.
[DEBUG] [0/DDC#1] Invalidating register interface
[DEBUG] [0/Radio#1] Invalidating register interface
[DEBUG] [0/Radio#0] Invalidating register interface
[DEBUG] [0/DUC#1] deinit() called, but not implemented.
[DEBUG] [0/DUC#1] Invalidating register interface
[DEBUG] [0/DDC#0] deinit() called, but not implemented.
[DEBUG] [0/DDC#0] Invalidating register interface
[DEBUG] [0/DUC#0] deinit() called, but not implemented.
[DEBUG] [0/DUC#0] Invalidating register interface
[DEBUG] [NIRIO] NI-RIO RX FIFO Transfer Check Quirk Disabled.
[DEBUG] [NIRIO] rpc_client stopping...
[DEBUG] [NIRIO] rpc_client stopped.
My questions:
- Is srsRAN correctly using the external clock? The debug logs always talks about an :internal" clock:
[INFO] [GPS] Found an internal GPSDO: LC_XO, Firmware Rev 0.932
[INFO] [X300] Radio 1x clock: 184.32 MHz
- What output am I supposed to see, when the external clock is correctly used? Or is it, and I am just misinterpreting the logs?
- What is better to use,
gpsdoor justexternal- and rely on the clock? I have both set to external. Usinggpsdogives a segfault because it fails to read the sensors, - but I assume that is because I dont have the required hardware for that..? - Are there any performance benefits (throughput?) when using a good external clock, like the one mentioned, rather than chosing
internal/default, and relying on the default CPU (?) clock?
I already looked at the official documentation, I just would like some clarification, because I still don't fully understand what is happening in the scenario above.
I am doing this troubleshooting still as part of an older issue I created, where the throughput is lower than I expected, - and I am wondering if using a proper external clock can have an impact on that.
Thanks.
Hi, any updates regarding this isssue?
We are facing a very similar problem with USRP B205mini. In our case we are using the REF IN, which we connect to a 1pps ref clock coming from GPS discipline oscilator.
However, we are also not sure if the external clock is being used since when we test it using the Signal Analyzer we've noticed that the transmission starts randomly at any time and not on the rise of the clock.
Thanks
Hi, any updates regarding this isssue?
We are facing a very similar problem with USRP B205mini. In our case we are using the REF IN, which we connect to a 1pps ref clock coming from GPS discipline oscilator.
However, we are also not sure if the external clock is being used since when we test it using the Signal Analyzer we've noticed that the transmission starts randomly at any time and not on the rise of the clock.
Thanks
Nope, I could not figure it out. Did you manage to get any new insights?