Unsupported frequency error generation

[acajic]

I'm not really sure if this is an issue with the code or with Vivado itself. I'm not that experienced with Vivado. I created a new project in Vivado 2020.2 and added your source files. I added the FIFO generator from the IP Catalog. However, I still see this

I'm not sure what it represents or how to get rid of it. Has anyone else encountered this?

[someone755]

This isn't part of Vivado or an issue with Xilinx IP. The error is raised on purpose, to prevent anyone from using a memory frequency that the project doesn't support, either non-JEDEC, or too high. It's given here https://github.com/someone755/ddr3-controller/blob/262f6b20bf1a1077399e024f4f47bfdee496a284/ddr3_x16_phy_params.vh#L87-L92

I wholeheartedly recommend you at least skim through the code. It's a relatively small file, but the work is not trivial. You'll need a top file where the controller will be instantiated. You can look at the sister branch to find an example top module for an example of a working instantiation.