ddr3-controller
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A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
I'm not really sure if this is an issue with the code or with Vivado itself. I'm not that experienced with Vivado. I created a new project in Vivado 2020.2...
Hello, I am very interested in this project, and I have met some problems in my study. I have instantiated the `ddr3_x16_phy_cust` and `ddr3_rdcal` modules in your Arty S7-50 project,...
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A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs