change MIG interface to AXI?

[12ff7a6]

Hi, I have already booted Ariane and NVDLA on VC707. Now I want to boot the same project on some other FPGA prototyping platform. Which means, I can't use Xilinx IPs. I found an open source DDR IP https://github.com/enjoy-digital/litedram But they do support AXI interface. ThenI found ESP is using native interface on DDR controller. Is that possible to change the native interface to AXI interface? So that I can replace the Xilinx DDR IP to open source IP. Thanks a lot!