slajerek
Bad Line Timings seem incorrect (shifted) when comparing to what the VIC2.txt states
Describe the bug Machine PAL, Bad Line, No sprites. running a program cycle by cycle when on a bad line, it looks like the bad line timings reported by The CPU counters are the following: 12 r/w cycles 3 w only cycles 40 cycles stolen by vic2 (43 if the above 3 w only cycles can't be used by any instruction) 8 r/w cycles
However, according to the vic2.txt doc (https://www.zimmers.net/cbmpics/cbm/c64/vic-ii.txt) the timings should be :
11 r/w cycles 3 w only cycles 40 cycles stolen by vic2 (43 if the above 3 w only cycles can't be used by any instruction) 9 r/w cycles
To Reproduce Steps to reproduce the behavior:
- Load the .prg in attachement
- run it using SYS4096
- Hit F10 to stop the execution
- Using the VIC2 screen, explore the CPU timings on raster line $83 (which is a badline) and notice the discrepancy that i have reflected in the big picture I have uploaded
Expected behavior Unless I'm wrong, according to the VIC2.txt doc, there should be 11 r/w cycles (not 12) at the beginning of the badline, and 9 r/w cycles (not 8) at the end of the badline.
Screenshots
Desktop (please complete the following information):
- OS: Windows 10
- Version : 0.64.68
Additional context
I have carefully reviewed the VIC2.txt file, and the very first "x" on the list belongs to cycle 63 which has been voluntary duplicated by the author on the left of the document (and cycle 1 has been also voluntary duplicated by the author on the right). Also based on the "phi" signal it's obvious the first "x" belongs to cycle 63 which has been duplicated.
Reviewing again and again I think i made an interpretation mistake : I assumed that because CC transitionned from 02 to 01 when transitionning VC from 0A (10) to 0B (11) meant that LDX#$08 had used cycle 11 as its very first cycle. Which is definitely wrong. Actually LDX #$08 starts at cycle 54 and ends at cycle 55. This means that we have :
cycles 0-10 (11 cycles) cycles 11-53 (43 cycles) - including our 3 W cycles cycles 54-62 - 9 cycles
It's all OK. I apologize for having misinterpreted the retrodebugger figures :/
@paich64 thanks!
OK! No worries, it happens to me also all the time :) Thanks for checking this carefully.
