Seppo Ingalsuo
Seppo Ingalsuo
> > > Just to clarify, is the topology going to support both 48+96kHz, or just 96kHz? The latter case is problematic, I have no real issues with the former....
> Removing the deep buffer from these 96 kHz topologies builds should be possible, I'll check it and update. Actually the deep buffer is already disabled with DEEPBUFFER_FW_DMA_MS=false. I just...
> > DEEPBUFFER_FW_DMA_MS=false > > Does this actually disable the deep buffer path or just default to the regular buffer size for the deep-buffer path? > > that's pretty bad......
> Ping @singalsu -- this pending ack from @plbossart and CI check is failing. @kv2019i Thanks for following this. The fail is because is CI at IPG has not updated...
Draft - there's also other bug to fix with no ramp happening at times.
Still, checking but looks like MCPS is not impacted. But need more tests to be sure. Here's switch control before and after:  ...
No updates, just rebase to restart CI.
> @singalsu Hmm, SDW MTL config has failed in SOF driver CI runs and when I look back, the same SDW target failed in previous PR testing (build ids 39443...
> Still draft ? Oops forgot, now ready!
No changes to patch, rebase and push again to restart CI. Note: DMIC and SSP blobs from topology can't work in LNL without this fix.