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Revert "neon riscv64: Enable RVV segment load/store only when we have…

Open Ruhung opened this issue 2 months ago • 0 comments

Previously, we applied this workaround to support CPUs that lack segment load/store instructions. To align with the current standard and because we no longer support simde on those CPUs, I reverted the PR.

This reverts commit 3e5facc1b69b1f97b9e84f8b70cb2ad7720729f6.

Ruhung avatar Oct 23 '25 13:10 Ruhung