This project has been upstreamed to chipsalliance/chisel3 and is no longer developed in this repository.

chisel-circt

Compile Chisel using CIRCT/MLIR

This library provides a ChiselStage-like interface for compiling a Chisel circuit using the MLIR-based FIRRTL Compiler (MFC) included in the llvm/circt project. This is an alternative to the Scala-based FIRRTL Compiler (SFC) that Chisel uses by default and is developed in chipsalliance/firrtl.

The MFC is a feature complete FIRRTL compiler, but does not support every annotation and custom transform-backed extension to Chisel.

If you suspect a CIRCT bug or have questions, you can file an issue on this repository, post on Discourse, or file an issue on CIRCT.

Setup

Include the following in your build.sbt. See the badges above for latest release or snapshot version.

libraryDependencies += "com.sifive" %% "chisel-circt" % "X.Y.Z"

Additionally, install CIRCT. You can either:

1. Build and install from source
2. Use a nightly docker image and the firtool script

After CIRCT installation is complete, you need firtool (the tool provided with CIRCT to compile FIRRTL circuits) on your path so chisel-circt can use it.

Base Project

Alternatively, a base project is provided in sifive/chisel-circt-demo.

Example

You can use circt.stage.ChiselStage almost exactly like chsel3.stage.ChiselStage. E.g., the following will compile a simple module using CIRCT.

import chisel3._

class Foo extends RawModule {
  val a = IO(Input(Bool()))
  val b = IO(Output(Bool()))

  b := ~a
}

/* Note: this is using circt.stage.ChiselStage */
val verilogString = circt.stage.ChiselStage.emitSystemVerilog(new Foo)

println(verilogString)
/** This will return:
  *
  * module Foo(
  *   input  a,
  *   output b);
  *
  *   assign b = ~a;
  * endmodule
  */