riscv_vhdl
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sergeykhbr
simulation of kc705_tb
Hello Serge, You have done great work in this project. I really appreciate it. However, I am now stuck in the simulation step of kc705 testbench. I followed these steps to simulate it. I have gone to kc705_sim directory and then run make build command and then make gui but it is not responding. It is displaying this message "make: srun: No such file or directory". Do you have any idea how to get it working? Thanks in advance.
Hi,
- srun is the executable binary of the Slurm utility. It is the resource manager used by a computer cluster. If you intend to run makefile on a single computer you need to remove srun and related arguments.
- To run kc705 simulation "as is" you need to know how to link Secure IP (SIP) library with you simulation utility. Xilinx doesn't provide SIP source code. KC705 DDR controller contains a lot of SIPs. Otherwise, asic_sim target uses only unisim components.
- I think the easiest solution for you will be to add SystemVerilog source and constrain files from folders (with sub-folders) sv, kc705 and kc705_sim to an empty Vivado project and use ISim simulator for simulation.
I have tried this solution but the simulation window is not even opening . It crashes from the beginning. Are there any certain configurations for the simulation in the make file? In addition, I have nullified the DRAM as I will not use it. Hence, I removed everything related to it in the testbench.
Not enough information. Not enough memory /CPU resources or something wrong with the port.
Hello again Serge,
it is working now. However, I have no idea why it is stopping at address 0 in the rom. Do you have any suggestions?
Looks good for me at this point. I've never tried to use ISim, do you see any messages in the vivado console or triggered breakpoint?
I think trying the make file is a good solution . However, To remove srun from the make file , Can I just comment all lines containing SRUN command. I am not familiar with srun actually , so it is really appreciated if you can help.
Moreover, I have nullified DDR component . Therefore , I think I do not need to link SIP with my simulation , right?
- Try to check input ports i_xmsto and i_xslvi of the axictrl_bus0 module that there're no 'X' values.
- Try to update to the latest version, some bugs were fixed on pnp-bus. They do not stuck the ncsim simulation but ISim could be more sensitive to that types of bugs.
I have just used it but it is the same output I think the problem is in cache as in my program v_resp_valid in instruction_cache is not set to 1 at all. I think this will affect the whole simulation . I do not know where the problem is actually but I think it must be set to 1 so that the fetch proceeds.
Could you try to update module axi2apb_bus1.sv file and try again? There was bug detected with the array index.
Can you please try to simulate it on xsim , So that I know that the problem is not in my environmnent? Thank you for your efforts
Hello Serge again,
I have found the bug that stopped the simulation. Here ctrl_path_id was displaying x value for me in simualtion and this causes the simulation to stop before filling first cache line . Hence , I think the problem is that vivado is considering ctrl_path_id=0 line to be another driver to ctrl_path_id . So, I have commented this line as shown and it is working right now . I know that it is in a process and it is sequential . However , I do not find any other possible reason . Finally thank you for your efforts
I'm glad that you found solution but I do not see there any functional changes. Last commit removes double assignments into process variable path_id, if this helps with ISim let it be here.
Can you please tell me which cache replacement policy you are using in the processor? Thank you