litex-template
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sergachev
ValueError: Cannot extract CSR name from code, need to specify.
make -f Makefile.kv260 load
Everything goes fine until LiteX Python script execution :
poetry run python lib/litex-boards/litex_boards/targets/xilinx_kv260.py
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2024-10-02 16:41:03)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xck26-sfvc784-2lv-c.
INFO:SoC:System clock: 100.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
Traceback (most recent call last):
File "/home/pascal/work/litex-template/lib/litex-boards/litex_boards/targets/xilinx_kv260.py", line 242, in <module>
main()
File "/home/pascal/work/litex-template/lib/litex-boards/litex_boards/targets/xilinx_kv260.py", line 225, in main
soc = BaseSoC(
^^^^^^^^
File "/home/pascal/work/litex-template/lib/litex-boards/litex_boards/targets/xilinx_kv260.py", line 67, in __init__
SoCCore.__init__(self, platform, sys_clk_freq,
File "/home/pascal/work/litex-template/lib/litex/litex/soc/integration/soc_core.py", line 181, in __init__
self.add_controller("ctrl")
File "/home/pascal/work/litex-template/lib/litex/litex/soc/integration/soc.py", line 834, in add_controller
setattr(self.submodules, name, SoCController(**kwargs))
^^^^^^^^^^^^^^^^^^^^^^^
File "/home/pascal/work/litex-template/lib/litex/litex/soc/integration/soc.py", line 682, in __init__
self._reset = CSRStorage(fields=[
^^^^^^^^^^^^^^^^^^^
File "/home/pascal/work/litex-template/lib/litex/litex/soc/interconnect/csr.py", line 383, in __init__
_CompoundCSR.__init__(self, size, name)
File "/home/pascal/work/litex-template/lib/litex/litex/soc/interconnect/csr.py", line 131, in __init__
_CSRBase.__init__(self, size, name)
File "/home/pascal/work/litex-template/lib/litex/litex/soc/interconnect/csr.py", line 50, in __init__
raise ValueError("Cannot extract CSR name from code, need to specify.")
ValueError: Cannot extract CSR name from code, need to specify.
make: *** [Makefile.kv260:26: build/xilinx_kv260/software/bios/bios.elf] Error 1
Have you met a similar error at some point?
The LiteX submodule is nearly 2 years old. I've simply updated LiteX-related submodules but I encountered other errors, LiteX BaseSoC have changed quite a lot in this time...
It may be easier to write a new script for my up-to-date LiteX setup, don't you think?
Same issue happened with the Zedboard script. I'm still investigating my issue :no_mouth:
I haven't been using and updating this repository for a while indeed but it works for me as is with a clean clone with all the registered git submodule versions:
make -f Makefile.kv260 load
poetry run python lib/litex-boards/litex_boards/targets/xilinx_kv260.py
INFO:SoC: __ _ __ _ __
INFO:SoC: / / (_) /____ | |/_/
INFO:SoC: / /__/ / __/ -_)> <
INFO:SoC: /____/_/\__/\__/_/|_|
INFO:SoC: Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2024-10-09 01:51:32)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : xck26-sfvc784-2lv-c.
INFO:SoC:System clock: 100.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x40000000, Mode: RW, Cached: False Linker: False.
INFO:SoCRegion:Region size rounded internally from 0xff20000000 to 0x10000000000.
INFO:SoCBusHandler:io1 Region added at Origin: 0xe0000000, Size: 0xff20000000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:master0 added as Bus Master.
INFO:SoCBusHandler:sram Region added at Origin: 0x00000000, Size: 0x80000000, Mode: RW, Cached: True Linker: False.
INFO:SoCBusHandler:rom Region added at Origin: 0xc0000000, Size: 0x04000000, Mode: RW, Cached: True Linker: True.
INFO:SoCBusHandler:csr Region added at Origin: 0xa0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:bridge added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectPointToPoint (1 <-> 1).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 1.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 2.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (2)
io0 : Origin: 0x80000000, Size: 0x40000000, Mode: RW, Cached: False Linker: False
io1 : Origin: 0xe0000000, Size: 0xff20000000, Mode: RW, Cached: False Linker: False
Bus Regions: (3)
sram : Origin: 0x00000000, Size: 0x80000000, Mode: RW, Cached: True Linker: False
csr : Origin: 0xa0000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
rom : Origin: 0xc0000000, Size: 0x04000000, Mode: RW, Cached: True Linker: True
Bus Masters: (1)
- master0
Bus Slaves: (1)
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (3)
- ctrl : 0
- identifier_mem : 1
- timer0 : 2
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
