Feature Request: System Verilog

[Beaker73]

The new verilog backend seems to support system verilog, based on the feedback I'm getting from the editor. But when trying to use structs I'll get the message that structs are not supported during compilation. I've even tried renaming with the *.sv extension but to no avail.

Would it be possible to enable system verilog compilation?

[sehugg]

Verilator has introduced some SV features; here's the docs on structs. Supporting structs should be possible, though since they are represented as a vector, I'd have to eliminate the 64-bit limit for them to be very useful.