sehugg
verilog - load binary data for chip-8 emulator
8 bit workshop is awesome!
I'm working on a Chip-8 emulator to run on an FPGA dev board I'm working on. and I'm making very rapid progress, as I don't need to go through a whole compile and download step, and get instant feedback from it.
One thing that would really help would be the ability to load in test data. I've tried the following:
module rom ( ... reg [7:0] rom [8191:0];
initial begin $readmemb("rom.txt", ram); end endmodule
This does seem to compile OK in 8 bit workshop, but nothing happens :( If I change the filename to something that's not uploaded, it does give an error, so I think it might work...
Could someone point me towards an example of how to do this if it is supported?
I think one issue is that it’s trying to read a “.txt” file as a binary. If it’s a binary ROM, upload it with an extension like .bin.
If it’s a hex dump, use ‘.hex’. See the Mango One project for an example of this:
https://github.com/sehugg/mango_one/blob/master/mango1.v I prefer binary files myself! Good luck!
On Mar 18, 2025, at 6:06 AM, Jacob Lister @.***> wrote:
jacoblister created an issue (sehugg/8bitworkshop#197) 8 bit workshop is awesome!
I'm working on a Chip-8 emulator to run on an FPGA dev board I'm working on. and I'm making very rapid progress, as I don't need to go through a whole compile and download step, and get instant feedback from it.
One thing that would really help would be the ability to load in test data. I've tried the following:
module rom ( ... reg [7:0] rom [8191:0];
initial begin $readmemb("rom.txt", ram); end endmodule
This does seem to compile OK in 8 bit workshop, but nothing happens :( If I change the filename to something that's not uploaded, it does give an error, so I think it might work...
Could someone point me towards an example of how to do this if it is supported?
1742293970157.jpg (view on web)
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jacoblister created an issue (sehugg/8bitworkshop#197) https://github.com/sehugg/8bitworkshop/issues/197 8 bit workshop is awesome!
I'm working on a Chip-8 emulator to run on an FPGA dev board I'm working on. and I'm making very rapid progress, as I don't need to go through a whole compile and download step, and get instant feedback from it.
One thing that would really help would be the ability to load in test data. I've tried the following:
module rom ( ... reg [7:0] rom [8191:0];
initial begin $readmemb("rom.txt", ram); end endmodule
This does seem to compile OK in 8 bit workshop, but nothing happens :( If I change the filename to something that's not uploaded, it does give an error, so I think it might work...
Could someone point me towards an example of how to do this if it is supported?
1742293970157.jpg (view on web) https://github.com/user-attachments/assets/9e86607d-3d81-46d8-a16e-ac7fea0797d5 — Reply to this email directly, view it on GitHub https://github.com/sehugg/8bitworkshop/issues/197, or unsubscribe https://github.com/notifications/unsubscribe-auth/AAAURH536NY4KFNQ3PYAYW32U743PAVCNFSM6AAAAABZH22K4KVHI2DSMVQWIX3LMV43ASLTON2WKOZSHEZDQMBZG42DOMA. You are receiving this because you are subscribed to this thread.
Thanks a lot!
I tried a few things, moving the $readmem from a submodule to the top level module seemed to fix it.
Definately keen to finish off writing a chip-8 emulator, and I don't think it's take long. I saw a few people requsting it the github issues/requests, so more than happy to contribute it if one dosn't exist already.
I have a gameboy emulator (TypeScript) I wouldn't mind reimplemeting in a HDL at some point as well.
I've uploaded the base repo here: https://github.com/jacoblister/ghostchip
One other quick question - I've set the repo up to build in 8bitworkshop and the VHDPlus envionrment https://vhdplus.com
I'm selecting the build bases on a verlog define like this:
ifdef WORKSHOP endif
Is there a predefined verilog `define I could use to pick up if it's building in the 8bitworkshop enviornent?
You have a few special 8bitworkshop #defines:
8BITWORKSHOP
EXT_INLINE_ASM
TOPMOD__
Good luck with your projects!
On Mar 23, 2025, at 5:39 AM, Jacob Lister @.***> wrote:
jacoblister left a comment (sehugg/8bitworkshop#197) Thanks a lot!
I tried a few things, moving the $readmem from a submodule to the top level module seemed to fix it.
Definately keen to finish off writing a chip-8 emulator, and I don't think it's take long. I saw a few people requsting it the github issues/requests, so more than happy to contribute it if one dosn't exist already.
I have a gameboy emulator (TypeScript) I wouldn't mind reimplemeting in a HDL at some point as well.
I've uploaded the base repo here: https://github.com/jacoblister/ghostchip
One other quick question - I've set the repo up to build in 8bitworkshop and the VHDPlus envionrment https://vhdplus.com
I'm selecting the build bases on a verlog define like this:
ifdef WORKSHOP endif
Is there a predefined verilog `define I could use to pick up if it's building in the 8bitworkshop enviornent?
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https://github.com/jacoblister/ghostchip https://vhdplus.com/ https://github.com/sehugg/8bitworkshop/issues/197#issuecomment-2746138956 https://github.com/notifications/unsubscribe-auth/AAAURH756VPKYWQAPM6PKOT2V2FP3AVCNFSM6AAAAABZH22K4KVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDONBWGEZTQOJVGY
jacoblister left a comment (sehugg/8bitworkshop#197) https://github.com/sehugg/8bitworkshop/issues/197#issuecomment-2746138956 Thanks a lot!
I tried a few things, moving the $readmem from a submodule to the top level module seemed to fix it.
Definately keen to finish off writing a chip-8 emulator, and I don't think it's take long. I saw a few people requsting it the github issues/requests, so more than happy to contribute it if one dosn't exist already.
I have a gameboy emulator (TypeScript) I wouldn't mind reimplemeting in a HDL at some point as well.
I've uploaded the base repo here: https://github.com/jacoblister/ghostchip
One other quick question - I've set the repo up to build in 8bitworkshop and the VHDPlus envionrment https://vhdplus.com https://vhdplus.com/ I'm selecting the build bases on a verlog define like this:
ifdef WORKSHOP endif
Is there a predefined verilog `define I could use to pick up if it's building in the 8bitworkshop enviornent?
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Thanks a lot @sehugg
I've got verilog chip8 going and running some test roms and the 'pong' program now.
you can see it by importing: https://github.com/jacoblister/ghostchip (main file is 'ghostchip_workshop.v')
I'm still having some strange issues with $readmemh -
in ghostchip_workshop.v - there are several commented out files for rom images that can be loaded successfully-
- sound.hex
- chip8logo.hex
- flags.hex
- keypad.hex
but if I try loading
- pong.hex
I get
Error: could not validate wasm module
the file 'pong.hex' is binary identical to 'sound.hex'. But for some reason the interpreter dosn't like it (filename maybe)?
I can work around it - but would be super helpful if you have any ideas? I tried on a couple of computers, after clearing cache etc.
Thanks.
Nice looking project! Haven't figured out what is up with WASM, but here's the error:
[wasm-validator error in function _initial__TOP__1] call param types must match, on [index.js:43:322](http://localhost:8000/node_modules/binaryen/index.js)
(call $$readmem_2 [index.js:43:322](http://localhost:8000/node_modules/binaryen/index.js)
(local.get $0) [index.js:43:322](http://localhost:8000/node_modules/binaryen/index.js)
(i64.const 8101815644102092152) [index.js:43:322](http://localhost:8000/node_modules/binaryen/index.js)
(i32.const 1085576) [index.js:43:322](http://localhost:8000/node_modules/binaryen/index.js)
) [index.js:43:322](http://localhost:8000/node_modules/binaryen/index.js)
(on argument 1)
Pretty strange, my initial thought is some weird internal Verilator optimization gone wrong.