Joachim Strömbergson
Joachim Strömbergson
The Verilator top level simulation seems not to work. We should debug and then add it to the CI flow.
Icarus Verilog is a mature and well used open source simulator with its own parser. It might be hard to build the application_fpga design due to the device specific modules....
Currently the FPGA design is "application_fpga". This name stems from when we also had an "interface_fpga". We should probably change the name to something better. This means updating file name,...
The core-level testbenches should be self testing. And they should return the correct exit code depending on if all test passed or not. If all tests passed, exit using finish()....
There are a few interesting linters, STAs that we could add to the CI flow to improve checks: Flawfinder https://dwheeler.com/flawfinder/ splint https://splint.org/ scan-build - exists as action in github https://clang-analyzer.llvm.org/scan-build.html...
It is quite possible that we could raise the clock frequency of the FPGA design. In order to do so we should analyze the timing after P&R and see what...
It is always good to get feedback from different tools. Other parsers, other synthesis, P&R tools. We haven't really done this. Lattice has the Diamond tools. We should push through...
## Description This PR implements a change to the existing timer to add a free running mode. This is currently an initial version. The testbenches has not been updated with...
For some applications a free running timer is needed. This if for example used to periodically check the timer to see if some measure of time has passed. With a...
## Description This is a Proof of Concept PR that tries to double the size of the FW_RAM by adding two more banks of instantiated block RAM. The change allocates...