sean-anderson-seco

Thank you for the quick review. > BTW, is this for RFE #17625? If so, please add `Closes #17625.` in the commit message. I did not write this specifically for...

> Commercial tools support merging the coverage for each source file (instead of by hierarchy/logic). It would be definitely good to add this type of coverage too. The report would...

> > Coverage for the state variable, to see if each state is tested. This is sort of like a specialized form of expression coverage. > > This one should...

OK, to illustrate the PSL point a bit further, ```vhdl type state_t is ( IDLE, START, DATA, STOP, ERR ); signal state: state_t; type trans_t is array (state_t, state_t) of...

> @sean-anderson-seco I have implemented the basic FSM coverage, @nickg just merged it. Looks good :)

For a workaround, you can serialize analysis only with something like ``` flock work-obj93.lock ghdl -a ... ``` This lets you parallelize other parts of the build (such as elaboration...

> According to the vhdl standard, there is an order of analysis, which is contradictory to concurrent analysis. Doesn't `--gen-depends` sufficiently specify the analysis order? If you have two modules...

Which is why I specified that neither module referenced the other. --- That said, if the order is so important, then analysis should all be done in one step so...

The order should of course be defined. That is, in your scenario, the dependencies should be something like ```make e: e.o a1.o a2.o e.o: e.vhd a1.o: a1.vhd e.o a2.o: a2.vhd...

> What should happen if the user then edits file `a1.vhd`? Should it be moved to the end, thus making it "dependent" on `a2.o`? Or should both a1 and a2...