improve RISC-V multi core boot

[axel-h]

• add much more comments
• fix SBI HSM register naming quirk
• Ensure DTB is always passed to primary core boot
• check SBI HSM error when bringing up secondary harts
• Stop wrong boot hart via HSM if possible
• unify stack definitions for all cores
• add multicore helper functions
• Drop variable hsm_exists, pass information as parameter
• Print more log messages

[yyshen]

@axel-h thanks for the changes. I just want to double check if there are any bugs fixed in the PR.