Debug port

[schoeberl]

Chisel 3 testers do not allow access to internal signals, so we need a debug port. However, this debug port should not be part of the generated hardware.

[keszocze]

You could do

class Lipsi(prog: String, debug: Boolean = false) extends Module {
  val io = IO(new Bundle {
    val dout = Output(UInt(8.W))
    val din = Input(UInt(8.W))
    val dbg = if (debug) Some(Output(new DebugData)) else None
  })

 if (debug) {
  io.dbg.get.accu := accuReg
  io.dbg.get.pc := pcReg
  io.dbg.get.exit := exitReg
 }

 // the rest
}

The None for the debug=false case will not be synthesized into actual hardware.

[schoeberl]

Yes, this is a good idea. HW is OK. I should change this. Or do you want to do it with a PR contributing your code ;-)

It is just a little bit ugly. I do not understand why we cannot access internal registers. During simulation all those internal signals can be dumped into the VCD waveform. So they are somehow accessible.

[keszocze]

Sure, I will prepare a PR.

I do agree about about the ugliness, but I fear that this is how it is supposed to be done.