Sameer Puri
Sameer Puri
> Is ALTERA_RESERVED_QIS setup by vendor tools automatically ? Yes, that comes with Intel FPGA tooling as far as I've seen. > Ok. Looks like Lattice Diamond also defines SYNTHESIS....
Hi @shreekumar3d , Would you be able to share the changes you made as a PR? We can build on top of it from there to support Lattice out of...
No worries!
Hi Jan, I'm not aware of any particular logic that would cause that. Could you share the changes you made to that code to use 24 bit audio? That way...
Hi mopplayer, Could you create a separate issue for this? Also, what model of TV/monitor are you using? On Wed, Sep 14, 2022, at 19:42, mopplayer wrote: > > >...
Hey, thanks for bringing this to my attention. I was not aware that SystemVerilog wouldn't work for Spartan 6. I'm most familiar with Quartus and Intel since that's what was...
Please give https://github.com/hdl-util/hdmi/tree/v1.2.1-verilog a try. I've converted to Verilog using [sv2v](https://github.com/zachjs/sv2v) and made sure it can compile. Let me know if you run into any problems!
Cool, let me know how it goes! On Fri, Apr 2, 2021, at 20:56, Antonio Sanchez wrote: > > Thanks a lot! I'm on it right now! > After solving...
Hey, thanks for the update. That's really unfortunate. If you are willing to share the source I can try to debug things in simulation from my end. On Wed, Apr...
~I have also run into this. It will eventually compile but seems it's much faster to use that flag, especially when debugging.~ Realized that because I was using lalrpop as...