2x accLat in timing cache

[Amin-Azar]

Hey,

to the best of my knowledge, ZSim models the timing (conventional) cache as if we need one accLat to access TAG and DATA arrays. however in newer designs, we need one for the TAG array and then another one for the DATA array. I have a way to get around this. Can anyone check this and tell me if it's OK to do so or no ?

1. In access(), instead of "cc->processEviction(..., respCycle);" I used: "cc->processEviction(..., respCycle+ accLat );" to push eviction events one accLat back.

2. If it is TAG_MISS we need no change, but for TAG_HIT I used "respCycle += accLat;" right before calling "getDoneCycle = respCycle; cc->processAccess(..., respCycle, &getDoneCycle);"

3. Finally, a hit will be " if (getDoneCycle - req.cycle == 2accLat) {...}" rather than "1accLat"

any thoughts on this ?