Robert Winkler

enhancement: Unions in DSLX language

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# Unions in DSLX language While working on DSLX designs, we found that adding unions could simplify the description of some design patterns, that currently require more elaborate implementation. We...

xls::dslx::ConvertOneFunction() fails to convert parametric functions

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The `xls::dslx::ConvertOneFunction` [docstring](https://github.com/google/xls/blob/1da08a2e3146a0708719a273119f24d56a8e2015/xls/dslx/ir_convert/ir_converter.h#L67) states that the `parametric_env` parameter can be used to provide bindings to use during conversion if the function is parametric. However, the function fails to convert parametric...

Add support for QuickLogic devices

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This PR adds support for the following QuickLogic devices: - EOS-S3 (https://www.quicklogic.com/products/eos-s3/) - PolarPro 3E (https://www.quicklogic.com/products/fpga/fpgas-sram/#polarpro3e)

This commit adds the next job to Travis CI, which produces the HTMLs of all the tests and deploys them to GitHub pages.

Add minimal target for Arty Board platform

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This commit adds a simple `minimal` target for the Arty board. The target is used to demonstrate the SymbiFlow toolchain usage with the `litex-buildenv` project. Custom target is needed since...

YoWASP yosys fails to generate SVG diagrams

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Currently, YoWASP Yosys fails to generate SVG diagrams. However, the `.dot` file is created correctly in the output directory. The problem seems to be related to `dot` execution: ``` 3....

Internal error during proc inlining

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**Describe the bug** Inlining a proc that spawns another proc and contains a logic that performs operations on tokens, causes an internal error. **To Reproduce** One can use the following...

modules/zstd: Add literals decoding

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This PR is meant to provide a proc implementing literals section decoding as described in: https://datatracker.ietf.org/doc/html/rfc8878#section-3.1.1.3.1 In the beginning, we will focus on implementing the entire RAW and RLE literals...

### What's hard to do? (limit 100 words) In DSLX, there is currently no way to verify data sent over channels without actually receiving it. This limitation requires modifying the...

### What's hard to do? (limit 100 words) Currently, interfacing DSLX designs with common communication buses (AXI, Wishbone, TileLink) is not possible. Adding support for these buses, along with logic...