aarch64-cpu
aarch64-cpu copied to clipboard
Low level access to processors using the AArch64 execution state.
Similar to [cortex-m-rt](https://github.com/rust-embedded/cortex-m/tree/master/cortex-m-rt), I'd like to help develop a runtime library for `aarch64-cpu`s. I've looked into some of the differences in how vector tables are setup, seems some people just...
I added the following registers by referring [here](https://developer.arm.com/documentation/ddi0601/2024-03/AArch64-Registers?lang=en). ## Added registers - CNTPOFF_EL2 - CPTR_EL2 - HPFAR_EL2 - ICC_CTLR_EL1 - ICC_SRE_EL2 - ICH_AP0R_EL2 - ICH_AP1R_EL2 - ICH_HCR_EL2 - ICH_LR_EL2 -...
And this is breaking my build - aarch64-cpu is the only crate that didn't update the dep. Please make a(n automated) release (pipeline).
Hi @andre-richter Thank you for maintaining this amazing project! This PR introduces a new interface (register HFGRTR_EL2) , This interface is currently being used in my new project [rust for...
Currently untested
Adds [MDCR_EL2](https://developer.arm.com/documentation/ddi0601/2025-09/AArch64-Registers/MDCR-EL2--Monitor-Debug-Configuration-Register--EL2-)
When running a AArch32 guest (EL1) under a AArch64 hypervisor (EL2) it is useful for the hypervisor to be able to access the registers of the guest, for example `SPSR_hyp`....
Some of the fields of [HCR_EL2](https://developer.arm.com/documentation/ddi0595/2021-06/AArch64-Registers/HCR-EL2--Hypervisor-Configuration-Register) are missing, this adds them.