Robin Heinemann

One more thing that might be interesting to think about (but not sure if this actually fits this issue) is where the PLL gets stored. Given there is usually only...

> Also, maybe we should supply the Platform when creating the PLL object, so that when we create an output clock, it would automatically add the corresponding period constraint so...

Oh whoops somehow that slipped my mind.

This is probably obvious, but access to the `locked` signal would be quite useful aswell.

### How should the user interface of `PackedStruct` and `Interface` look like; how does one create such a value? Currently I can think of atleast three different ways: 1. Using...

Something similar is also interesting for SoC's like the Zynq. It would be nice to be able to add a `PS7` instance to the platform, as well as maybe additional...

One thing that the RFC doesn't mention (but might be obvious) is, how the `@`-prefixed pins interact with the `conn` argument? With the connector system there is already one way...

@bhansconnect you can do something like this: ```python from nmigen import * from nmigen.back import pysim class Issue(Elaboratable): def __init__(self): self.rst = Signal() self.a = Signal() def elaborate(self, platform): m...

For my specifc problem it would be helpful to drive `Instance` io's from the simulator (for example to initiate AXI reads / writes coming from the `PS7`) and being able...

> Ah, so essentially you'd like the simulator to treat the ports of an unknown `Instance` as toplevel inputs and outputs, right? Correct. (or disconnect them, so the signals connected...