sample-project

sample-project copied to clipboard

Add hardware probe model to README

3

It'd be really helpful to people getting started with Rust and the RPi Nano to list what hardware probe model was used in testing this project and how to connect...

jhodapp

wire clk_sys to pll_sys, don't set refdiv (Fixes #5)

1

kahara

Source for clk_sys is not switched to pll_sys after PLLs are set up

1

To verify, looked at `CLK_SYS_CTRL` with debugger and it shows `0x00000000`, so the clock source is pointing to `clk_ref` as expected. And `CLK_SYS_SELECTED` shows `0x00000001` which, if I've interpreted the...

kahara

Sample example on wirting to UART using the PAC. TODO: The GPIO function select registers (funcsel) have the same name for all GPIOs, e.g. uart0_tx. This will not be fixed...

tacdom